PRESS RELEASE

Contact: Bob Fess
Aldec, Inc.
(702) 990-4400 ext. 227
bobf@aldec.com

FOR IMMEDIATE RELEASE

Henderson Nevada, March 12th, 2001 - Aldec announced today the formation of the HES Business Unit, which will pursue hardware/software co-design verification tools. The first products that have been released are based on a patented hardware embedded simulation process that makes hardware accelerators invisible to the user while achieving vastly improved simulator performance. The primary objective of the HES product line is to serve as an augmentation toolset to designers' current products, optimizing the productivity of their current software and hardware programs with no interference.

The HES Business Unit has been made into a discrete unit of Aldec; it has its own engineering, marketing and sales staff with a separate P/L center. The first products of the new HES Business Unit are hardware accelerators for AldecT, Cadence®, Mentor Graphics® and Synopsys® HDL simulators. Typical accelerations of these simulators is from 10 - 1000 times, which dramatically decreases design verification time of ASIC devices.

"Because of HES technology, people can now verify their SoC designs in a fraction of the time it took them with their simulators alone. HES dramatically accelerates designers' current simulators," stated Bob Fess, HES Business Unit Manager.

Using the PLI and FLI communications protocols, the HES hardware boards communicate with the HDL simulators on an event-by-event basis. The designer can swap modules in the simulator for modules in hardware and new modules can freely be added during simulation either to HDL or the hardware domain. This permits for the implementation of Incremental Design PrototypingT, which tests designs in successive segments rather than having to re-verify the design in its entirety each time.

HES hardware accelerators operate under UNIX, Linux and Windows NT and are fully compatible with products from Cadence, Model Technology and Aldec's RivieraT and Active-HDLT simulators. HES products can operate either as desktop stations or design verification servers, allowing effective teamwork on large SoC designs.

"Unlike emulators, the HES products do not require any setup. They install automatically and interface readily with all leading HDL simulators. We anticipate on rapid business growth," stated Bob Fess.

The business unit is currently pursuing an agreement with several government agencies as well as large semiconductor vendors and systems houses in the US, Europe and Japan to complement their current products with HES technology and optimize their design schedule through the accelerated verification system.

The new HES Business Unit is located in its own facility adjacent to Aldec's existing headquarters. Aldec implemented the HES unit in response to the growing complexity of SoC designs, as the HES product line economizes on design time and drastically accelerates time-to-market.

About Aldec
Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux, and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world.

Additional information about Aldec, Active-HDL, and HES is available at http://www.aldec.com.